1. Field of the Invention
The present invention relates to a pattern generation method, a computer-readable recording medium, and a semiconductor device manufacturing method.
2. Related Background Art
Recent advances in semiconductor manufacturing technologies have been remarkable, and semiconductor devices sized at a minimum processing dimension of 0.07 μm are mass-produced. Such miniaturization is enabled by significant progresses in micropattern forming techniques such as a mask process technique, a photolithographic technique and an etching technique. When the size of a pattern was great enough, a planar shape of an LSI pattern to be formed on a wafer was drawn as it is as a design pattern, a mask pattern faithful to the design pattern was generated, the mask pattern was transferred onto the wafer by a projection optical system, and a foundation was etched, such that a pattern substantially conforming with the design pattern could be formed on the wafer.
However, it is becoming more and more difficult to form a faithful pattern in each process along with the advance in the miniaturization of patterns, which has raised a problem of the inconformity of a finish dimension with that of a design pattern. In order to solve such a problem, techniques such as process proximity correction (PPC) or optical proximity correction (OPC) are used to generate a mask pattern different from a design pattern by taking into account the difference of conversion among processes so that a finish dimension may be equal to the dimension of the design pattern.
There are presently various discussions on next-generation lithographic techniques. While EUV exposure directed to shorter wavelengths has been lively discussed for the mass production of semiconductors sized at 0.03 μm, there are other proposals such as a multiple patterning process which combines an exposure apparatus presently used in mass production with a pattern formation method different from conventional methods.
In a sidewall mask manufacturing process which is one of the multiple patterning processes, a lithographic step and steps other than the lithographic step are combined together to form a pattern for forming a circuit pattern on a wafer. Thus, a resist pattern formed in the lithographic step diverges from a design circuit pattern. If a conventional design constraint is used which defines a line width and a space width in accordance with whether a resist pattern can be formed, it is difficult to design a circuit pattern, and a design constraint suitable to the sidewall mask manufacturing process is required.